This invention is in the field of machine emulation and especially concerns a source which emulates operation of a source CPU by translating source CPU instructions into target CPU instructions for issue and execution by a target CPU. More particularly, the invention relates to extensions of the emulation ability of such a system through the provision of means for accelerating the translating and issuing functions when source floating point arithmetic instructions are being emulated and which emulate the execution of source floating point RX-type instructions by execution of target register-to-register floating point arithmetic instructions.
Emulation is the imitation of the operation of a first ("source") CPU by a second ("target") CPU. The target CPU is specially programmed and architected to permit it to execute programs written for the source CPU. A program written for the source CPU comprises a sequence of source instructions which are provided, one-by-one, to the target CPU. The target CPU responds to each source instruction by executing one or more target instructions.
In U.S. Pat. No. 4,587,612 of Fisk et al., assigned to the present assignee and incorporated herein by reference, an emulation assist processor (EAP) receives a source instruction stream and maps each source instruction to one or more target instructions, the target instructions being passed to an instruction processing unit (IPU) of the target CPU. In the incorporated patent, the EAP converts multi-field source instructions into multi-field target instructions and streams the target instructions to the IPU for processing and issuing.
As is known, when the source CPU comprises a machine such as an IBM 370 host computer (described in U.S. Pat. No. 3,400,371, assigned to the present assignee, and incorporated herein by reference), the source instruction set includes multi-field floating point arithmetic instructions, primarily of the RX-type. Source instruction programs utilizing the IBM 370 instruction set characteristically are conditioned by the state of a condition code (CC), an indicator which is set according to the outcome of certain instructions among which are floating point arithmetic instructions. When an IBM 370 floating point instruction produces an abnormal outcome (such as an all zero result) or attempts an abnormal operation (divide by zero), an interrupt indicator is set which transfers control from the executing program to a supervisory routine for certain interrupt procedures. Emulation of the branching and interrupt features of an IBM 370 source program requires that the target program maintain condition code and interrupt indicators to effectively map program branches and interrupts.
While conceding that the branching and interrupt correspondence between source and target programs must be maintained, it is recognized that the speed of emulation can be enhanced by the ability to reliably predict the state of the condition code and interrupt indicators before the completion of executing floating point arithmetic operations. However, any such enhancement must account not only for the translation of source to target instructions, but also must take into account the issuance of converted target instructions.
One of the potential operational environments of the EAP of U.S. Pat. No. 4,587,612 imposes certain architectural bottlenecks affecting execution of target floating point instructions. In this regard, the instruction unit and floating point unit of the target CPU are interconnected by a 32-bit wide databus. When source RX-type floating point instructions are emulated, an operand denoted in the X field of the source instruction must be fetched from memory for provision to the FPU. Passage of the responsibility for obtaining the X-field operand from memory lengthens the instruction execution time. Execution of a target floating point instruction is further lengthened when the source instruction is an extended RX-type requiring two sequential memory accesses to obtain a 64-bit operand over the 32-bit databus.